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Characterization and Modeling of SOI RF integrated components
First Edition
The boom of mobile communications leads to an increasing request of low cost and low power mixed mode integrated circuits. Maturity of SOI technology, and recent progresses of MOSFET's microwave performances, explain the success of silicon as compared to III-V technologies for low-cost multigigahertz analog applications. The design of efficient circuits requires accurate, wide-band models for both active and passive elements. Within this frame, passive and active components fabricated in SOI technologies have been studied. Various topologies of integrated transmission lines, like Coplanar Waveguides or thin film microstrip lines, have been analyzed. Also, a new physical model of integrated inductors has been developed. This model, based on a coupled line analysis of square spiral inductors, is scalable and independent of the technology used. Inductors with various spacing between strips, conductor widths, or number of turns can be simulated on different multi-layered substrates. Each layer that composes the substrate is defined using its electrical properties (permittivity, permeability, conductivity).
The performances of integrated sub-micron MOSFETs are analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) are proposed to increase the performances of a CMOS technology for for analog, low power, low voltage, and microwave applications. They are studied from Low to High frequency.
The graded channel MOSFET is an asymmetric doped channel MOSFET's which bring solutions for the problems of premature drain break-down, hot carrier effects, and threshold voltage (Vth) roll-off issues in deep submicrometer devices. The GCMOS processing is fully compatible with the conventional SOI MOSFET process flow, with no additional steps needed. The dynamic threshold voltage MOS is a MOS transistor for which the gate and the body channel are tied together. All DTMOS electrical properties can be deduced from standard MOS theory by introducing Vbs = Vgs. The main advantage of DTMOS over conventional MOS is its higher drive current at low bias conditions. To keep the body to source current as low as possible, the body bias voltage must be kept lower than 0.7 V. It seems obvious that the DTMOS transistor is an attractive component for low voltage applications.
The performances of integrated sub-micron MOSFETs are analyzed. New alternative structures of transistor (the Graded Channel MOSFET and the Dynamic Threshold MOSFET) are proposed to increase the performances of a CMOS technology for for analog, low power, low voltage, and microwave applications. They are studied from Low to High frequency.
The graded channel MOSFET is an asymmetric doped channel MOSFET's which bring solutions for the problems of premature drain break-down, hot carrier effects, and threshold voltage (Vth) roll-off issues in deep submicrometer devices. The GCMOS processing is fully compatible with the conventional SOI MOSFET process flow, with no additional steps needed. The dynamic threshold voltage MOS is a MOS transistor for which the gate and the body channel are tied together. All DTMOS electrical properties can be deduced from standard MOS theory by introducing Vbs = Vgs. The main advantage of DTMOS over conventional MOS is its higher drive current at low bias conditions. To keep the body to source current as low as possible, the body bias voltage must be kept lower than 0.7 V. It seems obvious that the DTMOS transistor is an attractive component for low voltage applications.
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- In English
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- Publisher
- Presses universitaires de Louvain
- Title Part
-
Numéro 15
- Author
- Morin Dehan,
- Collection
- Thèses de l'École polytechnique de Louvain
- Language
- English
- Publisher Category
- Applied Sciences > Electricity
- Publisher Category
- Applied Sciences
- BISAC Subject Heading
- TEC000000 TECHNOLOGY & ENGINEERING
- Onix Audience Codes
- 06 Professional and scholarly
- CLIL (Version 2013-2019)
- 3069 TECHNIQUES ET SCIENCES APPLIQUEES
- Title First Published
- 2003
- Type of Work
- Thesis
Paperback
- Publication Date
- 01 January 2003
- ISBN-13
- 9782930344393
- Extent
- Main content page count : 232
- Code
- 2930344393
- Dimensions
- 16 x 24 x 1.3 cm
- Weight
- 348 grams
- List Price
- 18.60 €
- ONIX XML
- Version 2.1, Version 3
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Contents
Scientific publications vi
Introduction x
1 SOI technologies for analog applications 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Comparison of SOI and bulk MOSFET . . . . . . . . . . . . . . . . . . . 2
1.3 The SOI materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Structure and properties of the various SOI MOSFET transistors, the influence of the silicon film . . . . . . . . . . . . . . 5
1.3.1.1 Comparison between the structures of long channel FD and PD transistors . . . . . . . . . . . . . . . . . 5
1.3.1.2 Properties of FD and PD devices . . . . . . . . . . . . . 5
1.3.1.3 Threshold voltage . . . . . . . . . . . . . . . . . . . . . . 9
1.3.2 The position of industry . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Insulators and substrates used . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.1 Classical SOI substrate . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.2 High Resistivity SOI substrate . . . . . . . . . . . . . . . . . . . . 14
1.4.3 Silicon-on-Membrane . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.4 Silicon-on-Anything . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.5 Silicon-on-Sapphire . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5 Size Does Matter: Evolution of the Microelectronic . . . . . . . . . . . 17
1.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 On-wafer microwave measurement methods . . . . . . . 25
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Waves and scattering parameters . . . . . . . . . . . . . . . . . . . . . 25
2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.2 Power waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.3 Pseudo waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.4 Scattering Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.4.1 The transmission line . . . . . . . . . . . . . . . . . . . 31
2.2.4.2 The thru line . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.5 Transfer Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.6 Immittance Matrices . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.7 Change of reference impedance . . . . . . . . . . . . . . . . . . 37
2.2.7.1 Scattering Matrix . . . . . . . . . . . . . . . . . . . . . . 37
2.2.7.2 Pseudo scattering matrix . . . . . . . . . . . . . . . . . 38
2.2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3 The Vector Network Analyzer . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.2 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.2.1 The transfer function formalism . . . . . . . . . . . . 41
2.3.2.2 General TAN self calibration procedure . . . . . . . . 43
2.3.2.3 Practical applications . . . . . . . . . . . . . . . . . . . 47
2.4 On-wafer measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4.2 Measurement of silicon CMOS devices . . . . . . . . . . . . . . 50
2.4.2.1 Limitations due to CMOS technology . . . . . . . . . . 50
2.4.2.2 Two steps calibration . . . . . . . . . . . . . . . . . . . 50
2.4.2.3 Alternative to the two step calibration . . . . . . . . . 59
2.4.2.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.4.3 Optimization of the measurement procedure . . . . . . . . . . 60
2.4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.4.3.2 TRM Calibration . . . . . . . . . . . . . . . . . . . . . . . 61
2.4.3.3 On-wafer TRL Calibration . . . . . . . . . . . . . . . . . 63
2.4.3.4 In uence of the power . . . . . . . . . . . . . . . . . . . 65
2.4.3.5 Control of the quality of the calibration . . . . . . . . 65
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3 RF modeling and characterization of sub-micron MOSFET 69
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2 Small signal model of integrated SOI MOSFET . . . . . . . . . . . . . . 70
3.2.1 Useful e ect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2.2 Quasi-static model . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2.3 Non-quasi-static model . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2.4 Extrinsic model and access elements . . . . . . . . . . . . . . . 74
3.2.4.1 Extrinsic capacitances . . . . . . . . . . . . . . . . . . . 74
3.2.4.2 Extrinsic resistances and inductances . . . . . . . . . 75
3.2.4.3 Extrinsic-Extrinsic capacitances . . . . . . . . . . . . . 77
3.2.4.4 Access parameters . . . . . . . . . . . . . . . . . . . . . 79
3.3 Extraction procedure of the small signal model . . . . . . . . . . . . . 81
3.3.1 Parasitic access elements . . . . . . . . . . . . . . . . . . . . . . 81
3.3.2 Extrinsic-extrinsic capacitances . . . . . . . . . . . . . . . . . . 85
3.3.3 Extrinsic resistances and inductances . . . . . . . . . . . . . . . 88
3.3.4 Extrinsic capacitances . . . . . . . . . . . . . . . . . . . . . . . . 95
3.3.5 Intrinsic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.3.6 Comparison between FD, PD, and Bulk MOSFET . . . . . . . . 98
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4 Performances of alternative MOSFETs in SOI technologies 103
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2 Relevant gures of merit for RF applications . . . . . . . . . . . . . . 103
4.2.1 Figures of Merit of integrated transistors . . . . . . . . . . . . 104
4.2.2 Cut-o frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3 The Dynamic Threshold MOSFET . . . . . . . . . . . . . . . . . . . . . . 108
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.2 Device fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.3 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.4 Frequency behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3.4.1 Medium frequency . . . . . . . . . . . . . . . . . . . . . 114
4.3.4.2 High frequency . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.4 The Graded Channel MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.2 Device fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.4.3 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.3.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . 126
4.4.3.3 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.4.4 RF properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5 Passive elements on SOI technologies 143
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2 Properties of transmission lines . . . . . . . . . . . . . . . . . . . . . . 143
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2.2 Coplanar waveguide (CPW) . . . . . . . . . . . . . . . . . . . . . 144
5.2.3 Thin lm microstrip line (TFMS) . . . . . . . . . . . . . . . . . . 145
5.2.4 Strip line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.2.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.3 Modeling of integrated inductors . . . . . . . . . . . . . . . . . . . . . . 150
5.3.1 Topology under scope . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.2 De nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.2.1 Equivalent circuit . . . . . . . . . . . . . . . . . . . . . . 152
5.3.2.2 Quality factor . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.3 Modeling of square spiral inductors . . . . . . . . . . . . . . . . 160
5.3.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.3.3.2 Modeling 3-coupled lines on multilayered silicon substrate . . . . . . . . . . . . . . . . . . . . . . . . 165
5.3.3.3 Modeling of the admittance matrix of n-coupled lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.3.4 Modeling of the inductor . . . . . . . . . . . . . . . . . 171
5.3.3.5 Validation . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.3.3.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.3.4 Prospective design of square spiral inductor. . . . . . . . . . . 181
5.3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.3.4.2 Design rules . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.3.4.3 Prospecting new technologies . . . . . . . . . . . . . . 186
5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6 Conclusion 195
A Relations between scattering and immittance parameters I
B Determination of extrinsic-extrinsic capacitances III
C Alternative uses of the body contacted MOSFET VII
D Modeling of microstrip lines by using variational principle XI
D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XI
D.2 Using a variational principle . . . . . . . . . . . . . . . . . . . . . . . . . XI
D.3 Propagation modes determination of 3-coupled microstrip lines . . XIII