Memory devices based on floating-body effects (FBE) in Silicon-on-Insulator (SOI) technology are among the most promising candidates for sub-100nm and low power Dynamic Random Access Memory (DRAM). This new type of DRAMs, called Zero-Capacitor RAM (Z-RAM), uses only one transistor in partially-depleted (PD) SOI technology and takes advantage of FBE which have been considered as parasitic phenomena until now. The Z-RAM programming principles are based on the threshold voltage VTH variations induced by the excess or lack of majority carriers in the floating body.
In this dissertation, a new floating-body effect, the Transient Floating Body Potential Effect (TFBPE), based on the body majority carriers non-equilibrium and on the dual dynamic gate coupling in standard fully-depleted (FD) SOI MOSFETs is presented for the first time. The TFBPE occurs in a specific gate bias range and can induce strong hysteresis of the gate and drain current characteristics although the FD SOI transistors are usually known to be immune against the FBE and their aftermaths. Adapted from the same physics principles as in the drain current hysteresis, that we called the Meta-Stable Dip (MSD) effect, a new concept of one-transistor capacitor-less memory was also proposed, the Meta-Stable DRAM (MSDRAM) which is dedicated for double-gate operations.
All the experimental results and physics interpretations were supported by 2D numerical simulations. A 1D semi-analytical model of the body potential for non-equilibrium states was also proposed. For the first time, this original body-potential model takes into account the majority carriers density variations, i.e., the quasi-Fermi level non-equilibrium versus a transient gate voltage scan in a FD MOS device.